During the development and manufacture of electronic circuits, there is a need to vigorously test various designs and products before release to customers. Ideally, the performance of an electronic circuit, for example a microprocessor, is verified for all possible circumstances under which it might be operated in the real world. Unfortunately, this would involve exhaustively testing a potentially infinite number of machine operation sequences and therefore require a prohibitively long time to generate and run test sequences.
To sample a wide range of possible machine operation sequences for design verification, random instruction generators were developed. These systems simply generate a random sampling of instructions (typically in the microprocessor's assembly language) which is then converted to machine code and tested on the microprocessor. Typically the instructions that are tested are limited to those instructions that test the functionality of the microprocessor's internal units.
However, these generators suffer from several limitations. Although such systems can provide a wide range of possible microprocessor operations with minimal user input, they have no understanding of what operation sequences are likely to be encountered in the real world. Further, they do not understand which operation sequences might be most difficult for the microprocessor to handle. Thus, they sometimes fail to adequately test important aspects of a microprocessor's functioning.
Another limitation is that the functionality of the microprocessor in executing externally-generated requests cannot be tested. The current trend is for microprocessors to include a bus interface unit to handle data requests from devices connected to the microprocessor's external bus. The random instruction generators normally do not generate instructions to test the microprocessor's behavior in responding to these external devices.
Accordingly, there exists a need for a test verification system that can overcome these shortcomings.